# |
Authors |
Title |
54 |
Zeru Lan, Chunlu Wang, Pengfei Qiu, Yu Jin, Yihao Yang, Dongsheng Wang, Xiaoyong Li and Gang Qu |
AutoGuard: A Secure Implementation of the Conditional Branch Instruction |
12 |
Ville Yli-M?yry, Thomas Perianin and Sylvain Guilley |
Automated Search of Instructions Vulnerable to Fault Injection Attacks in Command Authorization Checks of a TPM 2.0 Implementation |
37 |
Bowen Hu, Weiyang He, Kuo Wang and Chip-Hong Chang |
A Black-Box Targeted Misclassification Attack on Edge AI With Adversarial Examples Generated From RAW Image Sensor Data |
14 |
Jiongzhe Su, Haoran Du, Quanhai Zhu, Mingtao Chen, Keyang Zhang, Bo Liu and Hao Cai |
Unveiling Security MRAM-OTP Macro using MTJ Hard Breakdown Mechanism |
32 |
Luke Beckwith, Huizhen Zhou, Jens-Peter Kaps and Kris Gaj |
Power Side-Channel Key Recovery Attack On a Hardware Implementation of BIKE |
13 |
Xinyuan Zhao, Yijun Cui, Fei Lyu, Chongyan Gu, Chenghua Wang and Weiqiang Liu |
High Reliable Processor-Based PUF on Voltage Over-Scaling Technique |
59 |
Meriem Mahar, Maamar Ouladj, Sylvain Guilley, Hacène Belbachir and Farid Mokrane |
Exact Template Attacks with Spectral Computation |
7 |
Anurag Kamal, Vishesh Mishra, Sparsh Mittal, Mahendra Rathor, Chandan Kumar and Urbi Chatterjee |
Sorting Attacks Resilient Authentication Protocol for CMOS Image Sensor Based PUF |
24 |
You Wang, Chaoyue Zhang, Yu Gong, Hao Cai and Weiqiang Liu |
Truly random number generation by using in-plane magnetic tunnel junction with weak anisotropy |
43 |
Muhammad Yasir Farooq, Haroon Waris, Nasir Mohyuddin, Sajid Baloch, Yu Gong and Weiqiang Liu |
Secure and Scalable UVM Verification Components (UVCs) to Accelerate Functional Verification of RISC-V based SoCs |
22 |
Rapha?l Comps, Jean-Baptiste Rigaud and Jean-Max Dutertre |
Analysis and Mitigation of Hybrid CMOS/MRAM DFF Vulnerabilities to Laser Fault Injection |
26 |
Tuan Kiet Dang, Trong-Thuc Hoang and Cong-Kha Pham |
A True Random Number Generator on FPGA with Jitter-Sampling by Ring Generator |
50 |
Haruka Hirata, Yusaku Harada, Yuko Hara-Azumi, Kazuo Sakiyama and Yang Li |
Yet Another Physical Leakage Assessment with the Wasserstein Distance |
28 |
Wen Wang and Peng Liu |
A Consistency Testing Method for Revealing RISC-V Processor's Undocumented Instructions |
55 |
Maoyuan Cai, Aijiao Cui and Yier Jin |
SecRiSBen: A RISC-V based SoC Benchmark for Evaluation of Security Verification Tools |
11 |
Tomosuke Ichioka, Yohei Watanabe and Yuko Hara |
PreLock: Precision Locking for Protecting Embedded Processor |
38 |
James Moore, Jack Miskelly, Maire O'Neill and Chongyan Gu |
A Novel FPGA Mutually Coupled Configurable Ring Oscillator PUF |
51 |
Kazuki Monta, Rikuu Hasegawa, Takafumi Oki, Takuya Wadatsumi, Takuji Miki, Makoto Nagata, Lang Lin and Norman Chang |
A Hybrid Simulation Approach for Accurate and Fast System-level Side-channel Leakage Evaluation |