Asian Hardware Oriented Security and Trust Symposium (AsianHOST) is an annual symposium which aims to facilitate the rapid growth of hardware-based security research and development. Another goal of this conference is to help build hardware security community in Asian and Pacific area.
|1||Hardware Security of Digital Image Filter IP Cores against Piracy using IP Seller’s Fingerprint Encrypted Amino Acid Biometric Sample||Regular|
|6||TrustSoC: Light and Efficient Heterogeneous SoC Architecture, Secure-by-design||Regular|
|8||Overtake: Achieving Meltdown-type Attacks with One Instruction||Regular|
|14||Emulating Covert Data Transmission on Heterogeneous SoCs||Regular|
|15||AHD-LAM: A New Mitigation Method against Voltage Drop Attacks in Multi-tenant FPGAs||Regular|
|16||A Lightweight and Machine-Learning-Resistant PUF framework based on Nonlinear Structure and Obfuscating Challenges||Regular|
|21||NNLeak: An AI-Oriented DNN Model Extraction Attack through Multi-Stage Side Channel Analysis||Regular|
|29||A Comparative Analysis between Karatsuba, Toom-Cook and NTT Multiplier for Polynomial Multiplication in NTRU on FPGA||Regular|
|30||Intrinsic Processor-based PUF Design for Approximate Computing: Faith or Reality?||Regular|
|31||A Hybrid Neural Network for Simultaneous Multi-Attack Detection in Sensor Networks||Regular|
|32||LLM4SecHW: Leavering Domain-Specific Large Language Model for Hardware Debugging||Regular|
|35||HeisenTrojans: They Are Not There Until They Are Triggered||Regular|
|37||When Memory Mappings Attack: On the (Mis)use of the ARM Cortex-M FPB Unit||Regular|
|38||A Lightweight Authentication Scheme with PE-Based Unclonable Label||Regular|
|44||DF-TEE: Trusted Execution Environment for Disaggregated Multi-FPGA Cloud Systems||Regular|
|7||Fault Analysis on AES and SM4 Through Automatic Property Extraction and Checking||Short|
|9||Tamper Resistant Design of Convolutional Neural Network Hardware Accelerator||Short|
|18||PMU-Data: Data Traces Could be Distinguished||Short|
|19||DDQ-APUF: A Highly Reliable Arbiter PUF Using Delay Difference Quantization||Short|
|33||A Comparison of One-class and Two-class Models for Ransomware Detection via Low-level Hardware Information||Short|
|39||A Compact Weak PUF Circuit Based on Random Process Deviations of Amplifier Chain||Short|
Hardware has long been viewed as a trusted party supporting the whole computer system
and is often treated as an abstract layer running instructions passed through the software layer.
Historically, cybersecurity community believed that the integrated circuit (IC) supply chain is well protected.
However, the IC supply chain, which is now spread around the globe, has become more vulnerable to attacks than before.
The heavy reliance on third-party resources/services breeds security concerns and
invalidates the illusion that attackers cannot easily access the isolated IC supply chain.
Formal methods have been proven to be effective in security verification on hardware code.
Trustworthy hardware is also under development for the construction of the root-of-trust.
The intrinsic properties of existing and emerging devices, MOSFET, memristor, spintronics, etc.
are leveraged for security primitives and applications.
Another trend in the hardware security area is the development of security enhanced hardware infrastructure for system level protection.
The goal is to provide a fully operational software and hardware platform that ensures secure design, manufacturing,
and deployment of modern computer systems.
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